It is well known that BiCMOS technology has the potential of combining the virtues of both of the two different types of transistors. Those skilled in the art have not been able to make optimal performance integrated circuits containing this combination because of the requirements for different processing. SOI device architectures allow the ultimate performance for both CMOS and bipolar transistors. However, it has been discovered (M. Yoshimi, et al "Electrical Properties and Technological Perspectives of Thin-Film SOI MOSFETS" IEICE trans, vol E74, no. Feb. 2, 1991, pp. 337-351) that superior SOI-CMOS scaling and performance can only be obtained if the silicon film thickness is 1,000 .ANG. or less. On the other hand, high performance SOI bipolar transistors require a silicon film thickness of about 1 .mu.m.
The art has not developed a method to accommodate the fact that CMOS circuits operate best in a shallow layer of silicon on oxide (SiO.sub.2) while bipolar circuits operate best in a much thicker layer. Clearly, a process that provided for the differing SOI silicon thickness requirements of CMOS and bipolar would enable both devices to have optimum performance.